1. Field of the Invention
The invention relates to a flip chip substrate, and more particularly, to a flip chip structure with two dielectric layers defining the chip conductive zone and passive component conductive zone on the surface of the substrate.
2. Description of the Prior Art
Accompanying the progress of movable electronic devices, several different types of packages, which are light, thin, and small, have been developed. The flip chip ball grid array (FCBGA) package is one example. The FCBGA package configuration differs from conventional ones particularly in that the semiconductor die is not connected to the package substrate through conductive pads and wire bonding, but is connected to the package substrate through solder bumps or conductive polymer bumps. Therefore, the flip chip package is capable of increasing the circuit layout density and increasing performance of circuitry.
The flip chip connection is an area array connection, so it is suitable for extremely dense configurations. It is easy to say that the flip chip connection is first forming the solder bumps on the electrode pad of the die, and then the die or the chip is put on the substrate. When the alignment of the conductive pad is correct. And then fabricating the reflow process, when the solder bumps are melted the solder bump due to their surface tension became balls shape. Finally, the chip and flip chip substrate are connected, which not only surmounts the conventional wire bonding method, but it also provides electrical efficiency due to shorter connection paths.
Please refer to FIG. 1 that is a schematic diagram of a flip chip ball grid array package configuration 10 according to the prior art. The FCBGA 10 includes a substrate 12 and a die 14, wherein the die 14 is connected on the conductive pads 21 of top-surface 16 of the substrate 12 by solder bumps 32. In addition, the FCBGA package configuration 10 further includes a plurality of surface mount pads 22 and a plurality of solder ball pads 24 deposited on the top-surface 16 and the bottom-surface 18 of the substrate 12 respectively, and two solder masks 26, 28 covering portions of the top-surface 16 and the bottom-surface 18 of the substrate 12 except the conductive pads 21, surface mount pads 22, and solder ball pads 24 respectively, for solder resist layers.
Furthermore, the surface of the die 14 has a plurality of electrode pads 30 deposited on corresponding conductive pads 21 of the substrate 12. A plurality of solder bumps 32 in the FCBGA package configuration 10 are deposited between the electrode pads 30 of the die 14 and the conductive pads 21 of the substrate 12, for forming the solder joint to fixing and electrically connecting to the die 14. An underfill layer 34 can be injected between the substrate 12 and the die 14, for protecting the FCBGA package configuration 10 from outside influences, and in-suit eliminating connection stress of the solder bumps 32.
After completing the FCBGA package configuration 10, the FCBGA package configuration 10 is mounted on the print circuit board (PCB) by a plurality of solder balls 36. Then the FCBGA package configuration 10 is electrically connected to the PCB.
Because a substrate is routed from a whole substrate plate according to the prior art, for enhancing the reliability and quality of connections of the substrate and die, the presolder must be added on each conductive pad of each substrate for connecting to each electrode pad of the die. However, when performing the presolder printing process, each substrate includes a variety of sizes and densities of conductive pads, such as first conductive pads formed on the chip conductive zone, and passive component conductive pads for the passive component conductive zone. Owing to said each substrate includes a variety of sizes and densities of conductive pads that the solder mask formed on the whole substrate plate is uneven or the substrate plate is warped. There are the reasons of the presolder printing process quality cannot be adequately controlled and causing different ball sizes, different quantities of presolders, solder ball falling off, and low process yield.